1. Field of the Invention
This invention relates generally to read-detection in solid-state storage devices (SSSDs). More particularly to methods and apparatus for detecting codewords stored in multi-level memory cells on readout of solid-state memory.
2. Description of Related Art
In solid-state memory such as flash memory and phase change memory (PCM), the fundamental storage unit (the “cell”) can be set to a number of different states or “levels”, which exhibit different electrical characteristics. These different levels can be used to store information. To readout the stored information, cell-level is detected via measurements that differentiate the different levels by exploiting the differing electrical characteristics. In “single-level cell” (SLC) devices, the memory cells can be set to only two levels and can record only binary values. Other devices have “multi-level cells” which can be set to q different levels, where q>2. For instance, multi-level NOR flash memories can store 4 levels, i.e. 2 bits, per cell. Multi-level cell (MLC) NAND flash memory chips that can store 3 bits of data per single flash cell using 25 nm process technology are currently available. Storage of 2 bits per cell in PCM chips has also been demonstrated.
When writing information to multi-level cells, each cell can be used to store a q-ary symbol with each of the q possible symbol values being represented by a different cell level. On readout of multi-level cells, the read signal level is compared with a set of reference signal levels indicative of the q cell-levels in order to determine which level each cell is set to and thus detect the stored symbol value. However, a problem in multi-level SSSDs is that the physical quantity measured during cell readout, such as electrical resistance in PCM devices, is liable to drift. In particular, the electrical resistance of PCM cells drifts upwards with time in a stochastic manner. This drift can be data-dependent and can vary for different cell levels. As another example, in flash memory cells the physical quantity measured is the transistor's threshold voltage. This threshold voltage drifts upwards as a function of the number of write/erase cycles the cell is subjected to. Thus, for any given stored symbol value and cell level, the actual read signal level obtained on cell-readout can vary. In situations like this where the read signal level distributions for cell-levels vary, the reference signal levels used for level detection need to be varied as well (e.g. with time, with the number of write cycles, or etc.), in order to ensure reliable detection of stored symbols.
A number of techniques have been proposed to address the problem of drift. One technique involves use of a fraction of the memory as a reference. A pool of memory cells is reserved for system use, and an earlier known information is written to some of these cells each time a block of user data is written in memory. Every time the user file is read, the reference cells are also read. As the stored cell-levels are known for the reference cells, and these cells have experienced the same usage as the user cells, the reference cell readings can be used to derive estimates for the changing reference signal levels used for detection. The drawbacks of this “reference-cell” method include: the overhead it entails, which translates to a loss of memory capacity; the penalty in terms of controller complexity and latency due to the readout of the extra cells, and issues related to the management of the pool of reference cells, e.g. wear-leveling issues. Also, because drift is a statistical phenomenon and there is significant variability between cells in a memory array, reference cells can not be representative and the effectiveness of reference-cell based approaches can vary substantially with time and over different portions of the memory array.
Model-based drift cancellation techniques seek to model drift based on key parameters such as temperature, time and wear, and compensate accordingly. It is, however, difficult to obtain an accurate cell history for the key parameters. There are also fluctuations from cell to cell and there is no well-established analytical model available for short-term drift. A model-based approach using time-aware sensing is described in “Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory”, Wei Xu at al., Proc. Int'l Symposium on Quality Electronic Design, 2010. The proposed system keeps track of elapsed time between writing and reading of memory cells and uses this to estimate, and compensate for, the impact of time-dependent drift.
A technique based on coding is detailed in our copending European Patent Application no. 10164495.3 (U.S. Patent Pub. No. 2011/0296274 A1). This technique encodes input data as N-symbol codewords of a so-called “translation-stable code”. Each codeword symbol can take one of q symbol values and is recorded in a respective q-level cell by setting the cell-level in accordance with symbol value. The translation-stable code is such that each possible input data word is mapped by the coding scheme to a codeword with a unique sequence of relative symbol values. Such a code can be constructed, for example, from codewords in a set of one or more permutation codes, each codeword of a permutation code being a particular permutation of a predefined vector (the “initial vector”) having N q-ary symbols arranged in order of increasing symbol value. In any case, with a translation stable code, information is effectively encoded in the relative, as opposed to the absolute, amplitudes of cell levels, and this feature imbues the scheme with a level of resistance to the effects of drift on detection accuracy.
Despite the previously-proposed measures, there is a need for improving read-detection techniques involving determination of reference signal levels for multilevel cell-levels that can be subject to drift effects.